1. Field of the Invention
The present invention relates to a MOS transistor circuit, and more particularly, it relates to a MOS transistor circuit which is applied to, e.g., an arithmetic and logic unit such as an adder.
2. Description of the Prior Art
FIG. 1 is a schematic block diagram showing general structure of a conventional adder. This adder is adapted to simultaneously add up multiple-bit data A and multiple-bit data B, and is formed by a plurality of full adders connected with each other through carry signal lines C. Each full adder receives a single bit of the data A and a single bit of the data B, to perform single-bit addition. For example, an n-th bit full adder FA.sub.n receives an n-th bit A.sub.n of the data A and an n-th bit B.sub.n of the data B. The n-th bit full adder FA.sub.n is connected with an (n-1)th bit full adder FA.sub.n-1 ahead thereof by a carry signal line C.sub.n-1 while being connected with an (n +1)th bit full adder FA.sub.n+1 subsequent thereto by a carry signal line C.sub.n. The respective full adders output the results S of addition. For example, the n-th bit full adder FA.sub.n outputs the result S.sub.n of addition. The result of addition of the data A and B can be obtained by summing the results S of addition of the respective full adders.
In the aforementioned adder, each of the full adders substantially adds up the data A and B and a carry signal from the full adder ahead thereof, to generate a carry signal on overflow and transmits the same to the subsequent full adder. The so-called Manchester type carry propagation circuit has generally been employed in order to propagate such carry signals. The Manchester type carry propagation circuit is disclosed in "Introduction to VLSI Systems" by C. Mead and L. Conway, 1980, Addison-Wesley Publishing Co.
FIG. 2 is a circuit diagram partially showing the structure of an (n-1)th bit, an n-th bit and an (n +1)th bit of the conventional Manchester type carry propagation circuit. With respect to the structure of the n-th bit as shown in FIG. 2, an exclusive OR gate 1.sub.n is supplied with an n-th bit A.sub.n of data A and an n-th bit B.sub.n of data B. Output 2.sub.n from the exclusive OR gate 1.sub.n is supplied as a propagate signal to the gate electrode of an n-MOS transistor 3.sub.n and one input of an exclusive OR gate 4.sub.n. The n-MOS transistor 3.sub.n, which is adapted to propagate the carry signal, is interposed between a carry signal line C.sub.n-1 from the (n-1)th bit and a carry signal line C.sub.n to the (n +1)th bit. The other input of the exclusive OR gate 4.sub.n is connected with a carry signal line C.sub.n-1 through an inverter 5.sub.n. The exclusive OR gate 4.sub.n outputs a sum signal S.sub.n, which represents the result of addition.
On the other hand, one input of a NOR gate 6.sub.n is supplied with an inverted signal A.sub.n of the n-th bit of the data A. The other input of the NOR gate 6.sub.n is supplied with an inverted signal B.sub.n of the n-th bit of the data B. Output 7.sub.n from the NOR gate 6.sub.n is supplied as a carry generate signal to the gate electrode of an n-MOS transistor 8.sub.n. One of conducting electrodes of the n-MOS transistor 8.sub.n is connected with the carry signal line C.sub.n and the other one is grounded through an n-MOS transistor 9.sub.n. The n-MOS transistor 9.sub.n is supplied in its gate electrode with a clock signal .phi.. These n-MOS transistors 8.sub.n and 9.sub.n form a second MOS transistor switching circuit for driving the carry signal line C.sub.n in response to the carry generate signal 7.sub.n. A p-MOS transistor 10.sub.n is interposed between a power supply V.sub.CC and the carry signal line C.sub.n, to be supplied with a clock signal .phi. in its gate electrode. The p-MOS transistor 10.sub.n forms a first MOS transistor switching circuit for precharging the potential of the carry signal line C.sub.n at the supply potential V.sub.CC.
While the above description has been made on the structure of the n-th bit, the remaining bits are similar in structure to the n-th bit. In FIG. 2, corresponding parts of the respective bits are indicated by the same reference numerals, subscripts of which are varied with the bits.
Description is now made on the operation of the conventional circuit. This circuit is controlled by the clock signal .phi. to operate in a precharge phase and a discharge phase. Further, it is assumed that the carry signal flowing through each carry signal line C indicates that a carry occurs at a low level.
The following description of the operation is made with attention drawn to the (n -1)th bit and the n-th bit, while it is to be noted that the other bits perform similar operation.
When the clock signal .phi. goes low, the circuit enters a precharge phase, so that the n-MOS transistors 9.sub.n and 9.sub.n-1 are turned off and the p-MOS transistors 10.sub.n and 10.sub.n-1 are turned on. Thus, the carry signal lines C.sub.n and C.sub.n-1 are precharged by the power supply V.sub.CC. The propagate signals 2.sub.n and 2.sub.n-1 and the carry generate signals 7.sub.n and 7.sub.n-1 are determined in the same phase.
Then, when the clock signal .phi. goes high, the circuit enters a discharge phase so that the n-MOS transistors 9.sub.n and 9.sub.n-1 are turned on and the p-MOS transistors 10.sub.n and 10.sub.n-1 are turned off. Consider such case where the n-bit carry generate signal 7.sub.n is at a low level and the (n -1)th bit carry generate signal 7.sub.n-1 is at a high level while the n-th bit propagate signal 2.sub.n is at a high level. At this time, the n-MOS transistor 8.sub.n is turned off and the n-MOS transistors 3.sub.n, 8.sub.n-1 and 9.sub.n-1 enter ON states. The electric charge on the carry signal line C.sub.n-1 is discharged to the ground through the n-MOS transistors 8.sub.n-1 and 9.sub.n-1, while the electric charge on the carry signal line C.sub.n is discharged to the ground through the n-MOS transistors 3.sub.n, 8.sub.n-1 and 9.sub.n-1. Thus, the carry signals are propagated from low-order bits to high-order bits.
The sum in the respective bits can be obtained by XORing the inverted carry signal and the propagate signal.
In the conventional Manchester type carry propagation circuit as hereinabove described, the propagate signal 2.sub.n is applied to the n-MOS transistor 3.sub.n for carry propagation to discharge the electric charge on the high-order bit carry signal line C.sub.n through the carry propagation n-MOS transistor 3.sub.n, thereby to propagate the carry signal. When the carry signal line C.sub.n-1 is at a high level, propagation of the carry signal from the carry signal line C.sub.n-1 to C.sub.n is not required since the carry signal line C.sub.n is already at a high level by precharging. When, on the other hand, the carry signal line C.sub.n-1 is at a low level, the electric charge on the carry signal line C.sub.n is discharged to the low-order bit through the n-MOS transistor 3.sub.n.
Consider such case where the carry signals are sequentially propagated to high-order bits. Even if the propagate signals of all bits simultaneously go high, considerable time is required by the resistance of the ON state of the carry propagation MOS transistors 3 when the carry signals are propagated through the multistage carry propagation transistors 3.
Although carry propagation velocity can be increased by reducing floating capacity of the carry signal lines C and decreasing the electric charges to be discharged, the potentials at the carry signal lines C are instabilized with respect to influence by other factors.